FIG. 1 illustrates a conventional processor memory system 100 including a memory controller 102 coupled to a plurality of processors 104 through an internal bus 106. The memory system 100 further includes a plurality of memory modules 108 (e.g., fully buffered dual in-line memory modules (FBDIMMs) that are in communication with the memory controller 102. In conventional processor memory systems, the latency for returned data (from a memory module) with respect to read operations is critical to the performance of attached processors. To help reduce this latency, the memory controller 102 includes early indication logic 110 that provides early information about the returning read data to a bus interface unit 112 in advance of the actual read data. Providing the early information in advance of the actual read data permits some pre-processing (e.g., buffer management, lookups, arbitration, and so on) associated with the read data to take place in the bus interface unit 112 and/or the internal bus 106. The early information (referred to herein as “early read indicators”) provided by the early indication logic 110 can include, e.g., a target buffer, a cache line position, or any special tagging or flags. Pre-processing of early read indicators permits the read data (upon arrival) to be passed to the internal bus 106 in a more time efficient manner.
In a memory controller, early read indicators are typically known well in advance of the returning read data, usually when a read command is issued to a memory module. To time-align early read indicators ahead of corresponding read data, conventional memory controllers typically includes an adjustable delay circuit. FIG. 2 illustrates a conventional pipeline-based adjustable delay circuit 200. In operation, the adjustable delay circuit 200 retrieves early read indicators from a read command stack 202 (or FIFO) several (clock) cycles before corresponding read data is to be returned. The early read indicators pass through a series of staged latches 204A-204D, with each latch 204A-204D feeding into a single multiplexer 206 that is controlled by a selection register 208. Controlling software writes the selection register 208 with a known value, which will select the proper staged latch that matches a desired delay. For example, if the early read indicators are selected from the latch 204D, the early read indicators will arrive coincident with the read data. If the early read indicators are pulled from the latch 204A, the early read indicators will arrive three clock cycles ahead of corresponding read data. FIG. 3 illustrates a conventional non-pipelined-based adjustable delay circuit 300. As shown in FIG. 3, early read indicators as well as a count (or return time) is stored into registers 302A-302D. The count is the time until the read data is returned—thus, the count decrements with each clock cycle, and when the count reaches zero, the read data is available. Comparators 304A-304D respectively compares the count stored in registers 302A-302D with a count stored in a selection register 306. Once the count stored in one of registers 302A-302D is less than the count stored in the selection register 304, the early read indicators are selected by a multiplexer 308 and passed forward, e.g., to a bus interface unit (not shown).
Conventional adjustable delay circuits as shown in FIGS. 2 and 3 are suitable for processor systems that contain a single clock domain. However, more complex memory systems are being developed that require memory controllers to interface with memories having different speed offerings, as well as interface with different processor and bus speeds. In such memory systems, the memory controller, the internal bus, and the processor (or processors) could all be operating in different clock domains at different speeds. In these memory systems, conventional techniques for providing an adjustable delay of early read indicators in which control software sets (or writes) a selection register does not work well. Such conventional techniques do not provide the needed ability to make dynamic updates. Furthermore, if the control software was used to make updates to a selection register, such a process could take considerable time and adversely affect performance of a memory system.